Moore's Law will continue, IMEC: The process design path from below 1nm to A2 has been formulated

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　　According to a report by eeNews, Luc van den Hove, CEO of the Belgian Microelectronics Research Center (IMEC), said at the Futures conference a few days ago that he believes that Moore’s law will not end, but that many parties need to make contributions together. In this regard, IMEC has proposed a path of semiconductor process technology and chip design from 1 nanometer to 2 angstroms (A2), so as to further continue Moore's Law.

　　The report pointed out that Luc van den Hove mentioned several generations of device architectures, from FinFET devices to interposer and atomic channel devices, as well as the introduction of new materials and ASML's High-NA exposure machine, which will take many years. The prototype equipment of the High-NA exposure machine currently being installed by ASML will be put into commercial use in 2024. According to Luc van den Hove, exposure tools will extend Moore's Law beyond the equivalent of the 1-nanometer node.

　　Luc van den Hove emphasized that in order to move towards more advanced processes, new device architectures need to be developed, as well as a push to scale down standard cells. On the basis that FinFET has become the mainstream technology from 10nm to 3nm, starting from 2nm, the GAA architecture composed of stacked nanosheets will be the most likely concept.

　　Luc van den Hove also mentioned the forksheet architecture developed by IMEC, "which allows us to connect the N and P channels more closely together with barrier materials, which would be an option for scaling gates beyond 1nm. Next, the N and P channels can be put together to scale even further, and we have developed the first versions of these architectures."

　　In addition, new materials using tungsten or molybdenum can produce structures equivalent to several atomic length gate.

　　At the same time, interconnect performance also needs to improve. “An interesting option is to move the power delivery to the backside of the wafer. This leaves more design flexibility for front-end interconnects. And all of these new materials and technologies are expected to lead to the next 15 to 20 years. Scale-up of chip manufacturing."

　　Luc van den Hove further pointed out that future SoC devices will use TSV and microbumping technology for 3D stacking of chips, and use different process chips to complete different tasks, so that multiple 3D chips need to be connected on a silicon interposer. .

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